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PID controllers with output signal selector

I am trying to configure two PID controllers whose outputs go to a single output signal selector for control of a valve. One of the controllers will be in normal use, while the other is a limit controller.

I have connected the backcalc output from the analogue output block to the backcalc in of the signal selector and the backcalc out from the signal selector to the backcalc in for each of the PID controllers. I would have expected this to prevent the non-selected controller from winding up to maximum under integral action. This is not happening. Is there something I need to modify in the PID controller to enable wind-up protection of the unselected controller.

I can of course construct some logic external to the PID controllers to perform this function, but I would have thought the output signal selector would inherently have this function.

Regards

Jeff Richards 

jeff richards
  • GeloCortez
    Thanks Andre and James for clarification.

    we had the same issue from the past (3 years ago) and DRL solved the issue - this was also suggested by our process experts.

    Will check the status propagation next time. Thanks again, cheers
  • JoshC

    In reply to Andre Dicaire:

    I understand the concern with having the control loop split into multiple control modules; however, an issue I have struggled with is how to handle faceplates and details if you place multiple PID function blocks in the same control module. To handle this, have you created custom faceplates and details that reference PID2, PID3, etc. ? It is a shame that the controller scheduling/execution isn't sophisticated enough to recognize when one control module is embedded in another and adjust the execution accordingly. I like how clean the programming looks when using multiple control modules for the same control loop (e.g. multiple loop override control).
  • neilrbrown
    I have watched this thread with interest as over-ride (or constraint) control is something I’ve come across a lot, and it’s not always done properly!  In my opinion, DeltaV handles this better than any of its competitors, even when the competing control loops have vastly different dynamics and hence tuning.  However, I very much agree with Josh on the single vs multiple module issue, and for much the same reasons – plus simplicity, standardisation and clarity from the operators’ viewpoint.  I like to put the control selector block (or nested blocks if required) downstream of the PID in the ‘normal’ control module.  The ‘over-ride’ (or ‘constraint’) controller(s) each have their own module, and these are configured much in the same way as cascade master controllers – with soft OUT and BKCAL input parameters, and yes, these MUST be ‘floating point with status’ as must the relevant constraint control input and BKCAL output parameters in the ‘normal’ module.  If required, the ‘normal’ controller faceplate and/or detail can be customised to show what is currently in control.  However, I find that it is usually enough to show this on the graphics.
     

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