FORCE_SP Operation state

I want to know if my EDC is being forced. There are three things i have to reference, EDC/FORCE_SP, EDC/MODE and the device options for 'Force_SP in CAS' and 'Force_SP in AUTO'. I can write a function to do so. Then I will also need to figure out the Device Opts bit string (probably trivial). 

Regardless, I'd rather just look at a different parameter, but I"m not sure if there is one. OPERATION_STATE is useful to know if I'm Interlocked or if No Permissive is true. But, it doesn't look like it contains a value for forced SP specifically.

THanks

  • In reply to TreyB:

    Force SP is a one shot deal. The triggering condition may still be true, but the EDC SP_D is free to be moved by the operator or by sequential logic. It would be problematic to have continuous writes to the CAS_IN_D or SP_D in CAS or AUTO, as these would undo the force write. The purpose of Force is to allow for some automatic actions on the EDC to support the Operator. LIke a Sump that needs to start on high level and stop on low level, but could be acted upon by the operator as needed. So there is no continuous force condition, except via an interlock.

    So are you wanting to indicate to the Operator that the last SP change was the result of a Force Setpoint write? Maybe that tells him why the motor is no longer running.

    If the Force SP expression can only go true if conditions are right for it to take action, and this is latched true until say the motor changes state. Maybe the state of the FORCE SP condition can be used? I I.e. ((Level <= 10) And (Motor <> STop)) OR ((FORCE_SP i = true) AND (Motor = stop)).

    The Force SP will ignore the force condition if the motor is stopped. If force condition is true, it is latched latched till the motor is started.

    Or something similar. Haven't tried this, but it creates a pulse state on the Force SP based a valid trap/clear condition. Another way is to break the FORCE condition out to create logic that goes true and clears and then use that bit in the Force Expression. Your icon follows the state of the logic. I used something similar in a CND block to apply a hysterysis on an analog trip, latching the trip condition with the CND output that cleared based on the second trip point. Worked nicely and this is the same approach. Assuming you can define the logic that clears the latch condition.

    Andre Dicaire